1. Field of the Invention
This invention relates to the field of semiconductor devices and more specifically to a process for forming a silicon dioxide (SiO.sub.2) interlevel dielectric layer on a semiconductor substrate, which fills gaps or cavities in the surface of the substrate to create a uniform planar surface over those gaps or cavities.
2. Prior Art
In the manufacture of semiconductor devices, there is a need to make electrical contact to certain regions of the surface of the substrate. Normally, a series of dielectric layers are formed on the surface of the silicon substrate which overlie the regions to be contacted. In order to expose these regions, an opening or via in the dielectric is formed. First, a photoresist mask which exposes the dielectric above the region to be contacted is formed. Next, the dielectric layer is etched to form a via which exposes the portions of the substrate to be contacted. Next, a layer of conductive material is deposited on the surface of the silicon substrate covering any overlying dielectric as well as regions exposed by openings in the dielectric, filling the vias. The conductive material is then covered with photoresist which is then patterned to cover the vias and what will be the "interconnects" or "interconnect lines". An etch step is then performed to remove the conductive material from the regions not covered, thereby leaving the conductive material in the vias as well as forming the interconnects. The interconnects electrically connect different device areas on the substrate and allow for electrical contact to external leads. Traditionally, sputtered aluminum (Al) has been used as the conductive material. Alternatively, a via fill step, whereby the via is filled with a conductive material such as a refractory metal or refractory metal silicide, is performed before the deposition of a top layer of aluminum, which is then patterned and etched to form interconnects.
In the manufacture of a semiconductor chip, many layers of dielectric material are generally applied to the semiconductor surface. A variety of methods and chemicals are used to form these dielectric films. One type of insulating film is formed by oxidation of tetraethyl siloxane ((SiOC.sub.2 H.sub.5).sub.4, more commonly known as tetraethyl orthosilicate (TEOS)) to form a SiO.sub.2 film on the semiconductor surface. Various methods can be used to oxidize TEOS so as to form silicon dioxide layers on semiconductor surfaces.
One of the best methods for deposition of TEOS films is known as chemical vapor deposition. This process forms a solid film on the substrate by the reaction of vapor phase chemicals on the semiconductor surface. Chemical vapor deposition processes are preferred over other methods because they are more economical and because they allow for easy control over the deposition process. Chemical vapor deposition methods give a high purity of deposited material. A great variety of chemical compositions can be deposited using chemical vapor deposition, some of which cannot be deposited with adequate film properties by any other method. Chemical vapor deposition processes use a reaction chamber into which the semiconductor wafer is placed. A given composition of reactive gases and inert gases are introduced into the reaction chamber. Upon reaction, these gases move onto the surface of the substrate. The reactive gases are then absorbed onto the substrate, migrating and undergoing film forming chemical reactions. Byproducts of the reaction are then removed from the reaction chamber by a vacuum. The energy which drives the reaction can be supplied by thermal methods, protons, or electrons.
Tetraethyl orthosilicate or TEOS is a material which is often used in chemical vapor deposition processes to form an SiO.sub.2 film to be used as a insulator on semiconductor devices. TEOS is used to produce a silicon dioxide film in both thermal chemical vapor deposition (THCVD) and plasma enhanced chemical vapor deposition (PECVD) processes.
THCVD is a thermally activated deposition process which is usually performed at or near atmospheric pressure. The use of THCVD TEOS to deposit silicon dioxide layers gives excellent step coverage, and the deposited silicon dioxide tends to fill in cavities and gaps between projecting surface features. Step coverage is determined by taking the minimum thickness of a deposited layer along a vertical substrate surface and comparing that thickness to the thickness of the deposited layer on the horizonal surface. The closer the vertical thickness is to the horizonal thickness, the better the step coverage. Disadvantages of THCVD methods include low deposition rates and high porosity of silicon dioxide formed by THCVD TEOS. Because of this high porosity, SiO.sub.2 formed by THCVD TEOS absorbs water during wet processing steps. This water, absorbed into the SiO.sub.2 pores will outgas during subsequent high temperature steps. THCVD TEOS cannot be used to deposit a SiO.sub.2 layer directly over interlevel metal layers because it will not adhere to the metal. Additionally, the THCVD process creates a high level of tensile stress in the metal which can cause the metal to crack.
Plasma Enhanced Chemical Vapor Deposition (PECVD) methods can also be used to deposit layers of SiO.sub.2 film. PECVD methods for applying TEOS give fast deposition rates and good step coverage. PECVD methods use a rf-induced glow discharge to transfer energy to the reactive gases. Silicon dioxide layers formed by PECVD TEOS are not highly porous, thus they do not outgas during high temperature steps. In prior art processes the semiconductor wafer is removed from the PEVCD reaction chamber before the deposition of subsequent SiO.sub.2 layers. Removal of the semiconductor wafer from the PEVCD reaction chamber will generally dry out or evaporate any accumulation of liquid TEOS which may remain on the wafer surface. Thus, accumulation of liquid TEOS on the wafer surface after PECVD processes has not generally been a problem in prior art processes.
When applying dielectric layers it is desirable to create a uniform surface, as close to a level, planar surface as possible, so as to facilitate the coverage of subsequent layers. In order to develop a uniform surface it is necessary to fill gaps between any protruding surface features. These surface features include devices, interconnect lines and interlevel metal layers. Though subsequent layers decrease the severity of these features, the cavities between features must be filled to obtain a uniform surface.
Due to the increasing density of VLSI devices the number of devices and surface features on any given semiconductor surface will continue to increase. This increase in the number of devices and surface features dictates that surface features must be spaced closer together, creating gaps between features of 1 micron or less. This close spacing creates highly irregular surfaces. When an SiO.sub.2 layer is deposited over these closely spaced gaps, the SiO.sub.2 will often from a thicker layer on the upper portions of the walls of the gap, causing the walls of the gap to meet during deposition. This creates a void in the bottom of the gap. The void will either contain gas or will be filled with moisture in subsequent wet processing steps. Upon later thermal processing steps, the moisture or the gas contained in the void expands, damaging the devices and the adjoining surface features.
SiO.sub.2 formed by PECVD TEOS cannot be used to fill gaps because it does not have sufficient step coverage. Deposition of TEOS by PECVD methods leaves gaps and cavities between surface features. SiO.sub.2 formed by THCVD TEOS can be used to fill cavities between surface features because SiO.sub.2 formed by THCVD TEOS gives better step coverage. Though it is good at filling gaps and cavities, it is porous. Subsequent processing generally includes at least one wet process step. In this step, water is absorbed into the pores of the silicon dioxide surface formed by THCVD TEOS. This water evaporates when layers of conductive material are deposited at high temperature causing outgassing. Upon via fill this outgassing causes irregularities in the filling metal and poor adhesion between the conductive material and the surface of the substrate. This phenomenon is known as "via poisoning."
One method for gap filling involves a series of PECVD TEOS SiO.sub.2 fills, each followed by an argon etch. The argon etch will remove more material from the upper sides of a cavity than from the bottom of the cavity. Thus, a series of etches and fills can be used to fill the cavity. But this process is slow and expensive, involving a large number of depositions and etches.
Other manufacturers of semiconductor devices use Spun-On-Glass (SOG) to fill gaps. SOG is applied over a layer of SiO.sub.2, formed by PECVD using silane chemistry (SiH.sub.4), in a series of steps, each of which deposits a thin layer of SOG which must then be baked and cleaned before the next layer is applied. After all layers are applied, a single plasma etch (based on flourine chemistry) is generally used to remove excess SOG. A second layer of PECVD SiO.sub.2 is usually deposited over the SOG. The use of SOG to fill gaps has been successful for gaps of 1 .mu.m and greater. When these gaps between surface features are less than 1 .mu.m, subsequent thermal processing steps will cause the SOG to crack and separation between layers will be observed. SOG will not flow into a cavity having an opening less than or equal to 0.3 .mu.m. Even if SOG were to flow into the cavity, the SOG would crack in subsequent thermal processing steps.
What is needed is a process for deposition of dielectric layers which will fill surface irregularities but will not create outgassing upon the via fill step. Preferably, this process for depositions of dielectric layers would be performed in one reaction chamber so as to avoid the addition of particulate contaminants to the wafer surface and to cut down processing time and expense.